The present invention relates generally to general purpose data terminals and, more particularly, to visual display control and data entry apparatus for use in general purpose terminals.
In the general purpose data terminal art, a general purpose terminal is used in conjunction with a host computer or microcomputer. The general purpose terminal provides keyboard means for entering data which is then relayed to the computer, and display means for displaying the data before it is relayed to the computer. The general purpose terminal also receives data from the computer and provides visual display means for display of information received from the computer. Some general purpose terminals have limited data manipulation capabilities.
The basic elements of the general purpose terminal include a received-character buffer, a transmit-character buffer, a visual display means, typically a cathode ray tube (CRT) for displaying the contents of a received character buffer, a keyboard for entering data into a transmit character buffer, and interface circuitry for communicatively coupling the received character buffer and transmit character buffer to a computer.
Communication between the data terminal and the computer is typically performed using standard universal synchronous asynchronous receiver transmitter (USART) links. When a USART link is used, communication between the data terminal and the computer is in serial data format.
Prior art general purpose terminals are typically limited to the transmit/receive functions described above. The art has been generally directed towards designing terminals strictly for transmission or reception of data from a host computer. As such, they are not designed to function directly with peripheral devices, such as floppy disk controllers. Therefore, prior art general purpose terminals typically access peripherals through the host computer. As such, valuable computer time must be used in order to access the peripheral. Additionally, software must be generated to permit the host computer to interface between the peripheral and the general purpose terminal. This results in higher cost and complexity.
Other areas of design emphasis in the general purpose terminal art have included visual display apparatus for the terminal.
In some terminals, the visual display is controlled largely by a CRT controller. Data entered displayed on the CRT is stored in a raster memory, in sequential fashion. The raster memory then contains all information being currently displayed on the display screen, and is addressed according to the location of the first bit of screen data. The CRT controll periodically reads out, or scans, the raster memory in order to refresh the visual display. Typically, this line refreshing is performed every 1/30 to 1/60 of a second. Line refreshing is required at these rates so that the display image appears constant and non-flickering to the human eye.
Data output from the raster memory is supplied to character generating means and video generating means which convert the binary data representing a particular character into a two-dimensional dot array (a number of rows high and a number of columns wide) for display on the CRT screen. Typically, up to eighty of these two-dimensional dot arrays can be strung together and displayed as a character line in the visual display.
In general, the visual display on a CRT screen is comprised of a number of horizontal scan lines spaced very close together so as to appear as a solid image. A character line is comprised of a number of scan lines. Data from the character generating means is generated scan-line by scan-line so that for a character line, the character generator will first send out the top scan line of the character line, then the next scan line of the character line, and so on until all scan lines which make up the character line have been sent.
Typically, the CRT controller also supplies a row count signal which tells the character generator which scan line of the current character line is being processed.
A character counter, starting at the location of the first bit of screen data contained in the raster memory, sequentially increments the address so that, as the scanning proceeds from left to right, the address of the character which is to occupy the particular character line position is sent to the raster memory. Data generated by the raster memory in response to this address is then sent to the character generator for generation of the data pattern, corresponding to the current scan line, for the particular character. The character counter is sequentially incremented in this manner until all of the screen data in the raster memory has been read out.
In such a configuration, line refreshing is performed on a full screen basis. That is, when the screen display is sought to be changed, the whole screen data section in the raster memory is rewritten. This results in added delay in modification of the display, as well as in increased difficulty in implementing any additional display features such as smooth scrolling, and double-height, and double-width characters. Control of the raster memory by the CRT controller as above lacks flexibility.
With the advent of the LSI microprocessor, more of the control function has been shifted from hardwired logic control to microprocessor control. Systems using microprocessors require external read-only memory (ROM), external random access memory (RAM), working memory, and associated interface circuitry.
Line refreshing in the typical microprocessing system is accomplished, when character attributes such as smooth scrolling and double-height and double-width, are desired, through the interaction of the central processing unit (CPU) of the microprocessor with the CRT controller, a translate RAM, a line counter, a screen memory RAM, and an associated multiplexer. In a non-smooth scrolling mode, the CRT controller provides the translate RAM with the starting address of the screen data that is stored in the screen memory RAM. The translate RAM, in response to CPU commands relays the character line address desired to be scanned to a line counter. The line counter sequentially increments the address to interrogate the screen memory RAM and to cause the desired data to be relayed to the CRT for display.
When the smooth scrolling feature is desired, the CPU supplies the translate RAM with the address of the character line at which the display is to start. The translate RAM then performs the address translation operations required for scrolling the addressed scan line data.
A multiplexer means is used to select between address information from the CPU and address information from the CRT controller. The selected address information is then routed to the translate RAM. The address information from the CRT controller is used when a normal display mode is desired. Additionally, when address data is multiplexed into the translate RAM, data emerging from the translate RAM and inserted into the line counter must be multiplexed with data coming from the CPU.
The above configuration requires the use of numerous additional hardware, as well as increases the complexity of control of the line refresh feature.
In the past, the ease with which a double height or double width character display feature could be implemented depended upon the type of line refresh technique used. When the CRT controller controlled the screen memory RAM directly by supplying the starting address of the screen information in the RAM, and then consecutively reading out the data, double height and double width features could not easily be implemented. For the double height feature, the contents of the screen memory RAM were required to be read out into another memory means, operated upon to modify the data, and then read back into the screen memory RAM for display by the CRT controller.
When the CPU/translate RAM/CRT controller arrangement was used, (the translate RAM contained the line attribute information) the double height feature was therefore implemented according to the contents of the translate RAM. As such, line attribute information within the translate RAM was required to be modified by the CPU, before a particular line of data could be displayed in modified attribute form.
In the past, information transfer between keyboard and main terminal has often been performed on a parallel data basis. For example, information was often communicated between keyboard and the main terminal body using parallel bit transfer. A four bit parallel address would be sent out to address a column of the keyboard, and four bit parallel data would be received from the keyboard in response. Three bits of this received data would represent the rows of the keyboard array, in which a key had been pushed. The fourth bit represented the logical Oring of the three bit row data in order to derive an interrupt signal to the terminal to signal that a key was ready for processing. In this configuration, serialization of the communication process was difficult.
Serial keyboard scanning in the typical general purpose terminal normally requires that substantial circuitry be resident within the keyboard in order to decode address data and interpret and encode the keyboard data for relay to the main terminal. As a result, numerous integrated circuits and associated hardware were considered a necessary part of the keyboard circuitry. The cost for such additional circuitry was high. At the very minimum, communication between the keyboard and the main terminal was performed using an output line for sending data in serial form, a clock line for receiving synchronizing pulses from the main terminal, and a control line for sending interrupt signals to the main terminal and for receiving control signals from the main terminal.